IBM's sub-1nm chip: what nanostack actually means

IBM just announced a 0.7 nanometer chip technology. That is roughly 7 angstroms, or about the width of three silicon atoms side by side. The press release claims nearly 100 billion transistors on a chip the size of a fingernail, 50% more performance or 70% better energy efficiency compared to their 2nm node, and at least a decade of future scaling ahead.

Those are big claims. Let me separate what is actually new from what is marketing, because the gap between those two things is wide.

What IBM actually built

The core innovation is called "nanostack," and it is a new transistor architecture. IBM invented the current leading-edge approach, called nanosheet, where the transistor channel is made of horizontal sheets of silicon stacked on top of each other. GAA (gate-all-around) transistors from Samsung and TSMC use variations of this idea.

Nanostack goes further. It vertically stacks and staggers transistors, layering them in 3D using what IBM calls "3D sequential integration." The key detail: each stacked layer can use different material combinations, so you can optimize the n-type and p-type transistors independently. That is not possible with the current planar approach, where both transistor types share the same substrate.

IBM experimentally validated this through three things: ultra-thin dielectric bonding in CMOS integration, dual-channel engineering, and functional CMOS inverter operation with expected switching performance. In plain terms, they proved the layers can bond, the two transistor types can be tuned separately, and the result actually computes. This is a research demo, not a product. But it is a real, working demo, not a simulation.

At VLSI 2026, IBM also showed that nanostack gives 40% scaling in SRAM. That matters because SRAM scaling has been the thing that breaks first. If you cannot shrink the SRAM cells, your logic density gains do not translate into better cache and your CPU stalls on memory waits. 40% SRAM scaling is genuinely good news for the next few generations of chips.

The performance numbers

IBM says the 0.7nm node delivers either 50% more performance or 70% better energy efficiency compared to their 2nm node, which they unveiled in 2021. There is an "or" in there because these are trade-offs: you can run the transistors faster at the same power, or you can run them at the same speed with less power. You do not get both at the same time, despite what the headlines suggest.

The 2nm comparison is IBM's own 2nm research node from 2021, not TSMC's or Samsung's production 2nm. IBM does not fabricate chips at volume anymore. They sold their fab to GlobalFoundries in 2015. These numbers are simulative projections from research silicon, which is perfectly normal in semiconductor research. But it means you should not directly compare these to TSMC's production 2nm numbers without a big caveat.

Why "sub-1nm" does not mean what you think

Semiconductor node names have not corresponded to physical dimensions in over a decade. TSMC's "3nm" process has transistor gates roughly 20nm long. "2nm" is not 2nm either. The node number is an industry shorthand for a generation of manufacturing technology, not a ruler measurement.

IBM's 0.7nm node, or 7 angstroms, follows the same convention. It means "the generation after what the industry is calling 1nm," not that any feature on the chip is literally 0.7nm wide. At that scale, you are talking about individual atom spacing, and you cannot reliably print structures that small with any lithography that exists today, including the High NA EUV tools IBM mentions in its press release.

The High NA EUV tool from ASML is real and is being installed at IBM's Albany research facility. It prints finer features than standard EUV. But even High NA EUV cannot print at 0.7nm pitch. The nanostack architecture is how you get more density without printing smaller: you stack transistors vertically instead of making them smaller horizontally. It is an architectural workaround, not a lithographic one.

The five-year wait

IBM says the earliest adoption of nanostack at the sub-1nm node could happen in as early as five years. "As early as" is doing a lot of work in that sentence. The semiconductor industry has a consistent track record of research-to-production timelines running 5-8 years for major architectural changes. TSMC went from GAA research papers to GAA production in about six years. Intel's 18A node is still ramping after years of delays.

Five years from now is 2031. By then, TSMC and Samsung will have shipped at least one more production node each. Whether nanostack keeps up with or leapfrogs those nodes depends on things IBM cannot control: yield rates, defect density, equipment availability, and whether the stacked transistor approach actually works at volume, not just on a research wafer.

IBM does not produce chips commercially. They license their technology to partners. Their Albany facility is a shared research hub with TEL, Lam Research, and SCREEN. The path from a research demo in Albany to chips in a data center goes through at least one partner's fab, and that fab has to re-tool for a completely new transistor architecture. That is expensive and slow.

What caught my attention

The 40% SRAM scaling result at VLSI 2026 is the most concrete thing in this announcement, and possibly the most important. SRAM has been the bottleneck for a while now. TSMC's N3 node barely shrinks SRAM compared to N5. If nanostack actually solves SRAM scaling for another node or two, that alone is worth the research investment, because AI workloads are memory-bound more often than they are compute-bound.

The independent material optimization per layer is also interesting. Right now, n-type and p-type transistors share the same silicon channel material. If you can put different materials in different layers, you can use high-mobility materials like germanium for p-type while keeping silicon for n-type. That is a real engineering advantage, not just a density trick.

I am less impressed by the "decade of scaling" claim. IBM has made similar claims at every node announcement. The physics is not the problem. The economics are. Building a High NA EUV tool costs hundreds of millions of dollars. A modern fab costs $20-30 billion. The question is not whether physics allows scaling. The question is who can afford to manufacture it.

What this means in practice, right now

For anyone buying chips in 2026: absolutely nothing. This is research, not a product. Your next laptop, phone, or server will not have nanostack transistors.

For anyone watching the industry: this is a signal that 3D sequential integration is becoming a mainstream research direction. Intel has been talking about backside power delivery and 3D stacking. TSMC is exploring similar approaches. IBM is the first to publicly demo a fully stacked transistor architecture at this node, but they will not be the only ones working on it. Expect similar announcements from other research groups within a year.

For people running AI workloads: the thing that will actually help you sooner is the SRAM scaling, if it makes it into production. More on-chip cache means less time waiting for memory, which means better tokens-per-second on inference and faster training iterations. That matters more than raw transistor count for the kind of work most readers of this blog are doing.

The Apple price increase that hit the same day is a useful contrast. Apple is raising MacBook and iPad prices because memory costs are going up. The current generation of chips is getting more expensive, not cheaper. IBM's nanostack is a bet that the next generation reverses that trend. But it is a bet, not a guarantee. And it is years away from showing up in anything you can buy.